OV-TEST-INDEX · v1.1 · 2026-09-27Download PDF
| Doctype | Index |
|---|---|
| Doc id | OV-TEST-INDEX |
| Product line | openvvvf |
| Applies to | openvvvf-control-module, chassis-size-2 |
| Version | 1.1 |
| Date | 2026-09-27 |
| Description | Formal test reports and validation evidence for OpenVVVF hardware, firmware, and integration. |
| Nav order | 340 |
Testing and Validation
This section contains formal test records and validation evidence. Each document is evidence that a specific feature, requirement, or hazard mitigation was exercised.
All hardware power tests follow the shared definitions and evidence requirements of the Hardware Test Methodology — steady-state criteria, calculated quantities (P/Q/PF/efficiency), reconciliation rules, and naming.
Test evidence dashboard
Hardware
| Test ID | Name | Motor class | Status | Trace | Report |
|---|---|---|---|---|---|
| 1 | PMSM Resistance Calibration Validation | PMSM | draft | motor self-commissioning / calibration routine | Report |
| 2 | PMSM Inductance Calibration Validation | PMSM | draft | motor self-commissioning / calibration routine | Report |
| 3 | Power Resistor Sanity Check | - | draft | motor self-commissioning / calibration routine | Report |
| 4 | Induction Motor Testbed | Induction | draft | motor self-commissioning / calibration routine | Report |
| 5 | Induction Motor Resistance Calibration Validation | Induction | draft | motor self-commissioning / calibration routine | Report |
| 6 | Inductance Calibration Validation | Induction | draft | motor self-commissioning / calibration routine | Report |
| 7 | Induction Motor 1-Hour No-Load Test | Induction | draft | gate-driver switching / thermal baseline | Report |
| 8 | Induction Motor 180 V Power Stage Bring-up | Induction | draft | power-stage bring-up at elevated bus voltage | Report |
| 9 | Induction Motor 180 V 20-Minute Reversal Test | Induction | draft | direction-change sequencing / current control | Report |
| 10 | Motor Self-Commissioning Accuracy Report | PMSM + Induction | draft | motor self-commissioning / calibration routine | Report |
| 11 | Gen7 Board Temperature Sensor Validation | - | draft | board temperature sensing / ADC measurement chain (OV-TEST-HW-GEN7-TEMP-NTC-VALIDATION) | Report |
| 12 | Low-Power Regen 100 A Phase-Current Endurance (No Cooling) | Induction | draft | high-current regen endurance / phase-current capability at low DC-bus voltage (no cooling) | Report |
| 13 | 200 A Regen to 79 °C — Gen7 Size 2 | Induction | draft | high-current regen staircase; thermal rise with dry heatsink interface | Report |
| 14 | Thermal OTP Trip — 200 A Regen, Gen7 Size 2 | Induction | draft | overtemperature protection chain validation (trip at ~80 °C baseplate) | Report |
| 15 | Initial 400 A Regen Test — Gen7 Size 2 | Induction | draft | 400 A phase-current capability with bus clamp; current-clamp saturation identified as measurement artifact | Report |
| 16 | 450 A / 13 kW Regen — Gen7 Size 2 | Induction | draft | 450 A phase-current capability at ~150 V clamp; OT trip reproduced | Report |
| 17 | 200 A Regen Steady-State Thermal Test — Gen7 Size 2 | PMSM | draft | continuous-duty validation of the thermally-pasted interface (54.7 min, plateau 44.4/44.0 °C) | Report |
| 18 | 200 A Motoring Steady-State Thermal Test — Gen7 Size 2 | PMSM | draft | motoring-direction counterpart of test 17 (42 min, plateau 43.6/43.5 °C) | Report |
| 19 | 300 A Regen Steady-State Thermal Test — Gen7 Size 2 | PMSM | draft | 300 A continuous regen at ~2,600 RPM (22.9 min, 11.7 kW, plateau 63.2/61.7 °C; stopped on machine limit) | Report |
| 20 | SSO Pathway Latency — Gen7 Size 2, Low Bus | PMSM | draft | fault→six-switch-open latency (SG-03/SG-13, FSR-05): gate-driver fault ≤10 ms bound; ADC watchdog ISR break, bounded 30.3 A trip; physical pathways deferred | Report |
| 21 | SSO Gate-Drive Kill Pathways — Gen7 Size 2, Low Bus | PMSM | draft | Path 2a gate-power kill + Path 4 reset assertion (SG-03/SG-13, FSR-05): as-found no detection, gate-loss + TorqueLoss detectors added, retested to pass (flags ≤0.3 s) | Report |
| 22 | Over-Torque Watchdog — 55 A Trip, Locked Rotor, Gen7 Size 2 | PMSM | draft | SG-06/FSR-07: 110 %-of-calibrated-max over-torque chain implemented fix-forward; trip at 55.0 A vs 50 A max, 3× repeatable, SSO ≈0.6 ms, derived AWD backstop | Report |
| 23 | Rotor Feedback Loss Detection — Gen7 Size 2, Low Bus | PMSM | draft | SG-08/FSR-09: hard sin/cos disconnect at −2190 RPM → SSO µs–10 ms via all-channel AWD; blind-start defect fixed (start refusal), Critical EncoderLoss chain added; layered detection documented | Report |
| 24 | DC-Link OV/UV Protection — Threshold Injection, Gen7 Size 2 | PMSM | draft | SG-10/FSR-11/FSR-21: all four transitions validated at 49 V by threshold injection; OV-warning regen-disable + UV derate implemented fix-forward; critical OV/UV SSO ≪50 ms; FSR-21 candidate thresholds recorded | Report |
| 25 | DESAT / Gate-Driver FLT Protection — Pulse Injection, Gen7 Size 2 | PMSM | draft | SG-12/SG-14/FSR-13: 50 V ≥800 A no-DESAT bound; 100 V winding pulses → driver /FLT; FLT→MCU blindness (missing BIE/NVIC) fixed, latched PwmBreak + SSO verified; coproc FLT path open | Report |
These reports validate the calibration routines on the C2 test fixture. The same routines are used on all OpenVVVF chassis; add a new report only when a different motor or harness is introduced.
Safety-mechanism validation
| Test ID | Name | Scope | Status | Trace | Plan |
|---|---|---|---|---|---|
| - | Fault-Injection Test Plan | component / system / integration / environmental fault injection (control module + power stage) | planned | HARA safety goals, FSRs, hazards | Plan |
| - | Vibration Test Plan | mechanical/environmental random vibration (control module + C2 power stage assembly) | planned | HARA failure modes relying on connectors/harness; fault-injection E-01 | Plan |
| - | Thermal Test Plan | hardware thermal characterization + firmware thermal behavior (FSR-08 derate/SSO), C2 power stage | planned | OV-C2-DD-THERMAL, OV-C2-DD-DCLINK-THERMAL, FSR-08 | Plan |
The fault-injection plan spans all test domains, so it is filed directly under Testing. Execution campaigns produce dated test reports filed as siblings of the plan, referencing it by test ID.
Domains
Documents are filed by what is being tested, not by what equipment the bench uses:
- Hardware - The DUT is physical hardware: power-stage bring-up, thermal, and bench characterization. Firmware-routine validations whose error budget is power-stage physics (e.g. motor self-commissioning calibrated against instruments) also live here.
- Firmware - The DUT is control-module firmware logic: unit tests and host- or bench-based tests that do not inject physical faults.
- Integration - System-level tests combining control module and power stage.