System Thermal Analysis

This document estimates the total heat dissipated into the heatsink by the 3-phase traction inverter power stage (3× Mitsubishi CM600DY-24T half-bridge IGBT modules plus the DC-link capacitor bank) and derives the heatsink thermal resistance required for continuous operation. It is the sizing input for the custom heatsink design.

Value marking convention used throughout:

• [DS] - value taken directly from the CM600DY-24T datasheet (Mitsubishi Electric, publication date December 2020); page/figure cited.
• [EST] - engineering estimate derived from datasheet curves (digitized) or standard scaling laws; not explicitly guaranteed by the datasheet.
• [ASM] - modeling assumption about the operating point.

Nomenclature

References and system inputs

• CM600DY-24T datasheet, Mitsubishi Electric, December 2020 (600 A / 1200 V dual (half-bridge) IGBT module, 62 mm package).
• OV-C2-DD-DCLINK-THERMAL - DC-link capacitor bank heat load of ≈40 W at rated ripple, rejected to the heatsink through the standoff/spreader-plate path.
• Project README - power stage: 3× CM600DY-24T half-bridge modules (one per phase), SVPWM, DC link 102–320 V (140 V nominal), 600 A class output. Gate drive +15 V / −9 V via onsemi NCV57100 (7 A peak gate current class).
• Hardware designer input (2026-08, v1.1/v1.2): populated external gate resistance $R_G = 2.7 \ \Omega$ (not the 1.0 Ω datasheet test condition); PWM is clamped at 6 kHz maximum (v1.2). 2 kHz is not the operating intent, 16 kHz will not be used, and the 8 kHz point is dropped: it sits next to the ~7.8 kHz series resonance of the electrolytic can branch (OV-C2-DD-DCLINK-RIPPLE) and is unattractive anyway; 8 kHz rows are kept in the tables for reference only, outside the clamped envelope.
• Current convention (v1.3 correction): the "600 A" design figure is peak phase current, not RMS. The design point is 600 A peak = 424 A RMS ($\hat{I} = 600$ A). All design-point loss/temperature tables in this revision are evaluated at 424 A RMS; current-sweep tables are labeled in RMS with the peak equivalent noted where relevant.
• OV-C2-DD-DCLINK-RIPPLE - DC-link ripple derivation: bank ripple is 0.511 A RMS per amp of phase current (RMS); the 60-can electrolytic bank is ripple-limited above ~330 A RMS (~465 A peak) continuous. Basis for the continuous/peak rating in §6.4.

Datasheet parameters used (CM600DY-24T)

Ratings and electrical characteristics

Thermal resistances

Note: $R_{th(c-s)}$ is a typical value; no maximum is given. Grease ageing/pump-out (datasheet note 8) can raise it over life - covered by the heatsink margin policy in §6.

Device model parameters digitized from datasheet curves

Conduction models use the standard $V_0 + r \cdot I$ straight-line fit to the datasheet output/saturation curves at $T_{vj} = 125 \ ^\circ\text{C}$ (chip values), with the internal lead resistance $R_{CC'+EE'} = 0.3 \ \text{m}\Omega$ added because it dissipates heat inside the module:

Switching energy models (datasheet p.7, "Half-Bridge Switching Characteristics - switching energy vs collector/emitter current", $V_{CC} = 600$ V, $V_{GE} = \pm 15$ V, $R_G = 1.0 \ \Omega$; the solid $T_{vj} = 150 \ ^\circ\text{C}$ curves were used, anchored exactly at the p.2 table values at 600 A; the dashed 125 °C curves lie ≈5–10 % lower, so the 150 °C curves are conservative at the 125 °C operating point):

Piecewise-linear interpolation of these anchor points is used in the model. Digitization uncertainty is about ±5 % (line thickness / anti-aliasing). Note $E_{on}$ is markedly superlinear above 600 A, and $E_{rr}$ saturates above ≈700 A.

Scaling laws applied (not given in the datasheet):

• Voltage scaling: $E(V_{DC}) = E_{600\text{V}} \cdot (V_{DC} / 600 \ \text{V})$. Standard first-order scaling of switching energy with bus voltage. [EST]
• Temperature: 150 °C energy curves used at the 125 °C operating point (conservative). Conduction parameters at 125 °C. [EST]
• Gate conditions: datasheet energies are at $V_{GE} = \pm 15$ V and $R_G = 1.0 \ \Omega$; the inverter drives +15 V / −9 V with a populated $R_G = 2.7 \ \Omega$. The $V_{GE(off)} = -9$ V vs −15 V difference is assumed negligible for the energies. The $R_G$ increase is corrected as follows: the datasheet p.7 $E$ vs $R_G$ figure shows $E_{on}$ roughly tripling at $R_G = 10 \ \Omega$; interpolating linearly in $R_G$ between the 1.0 Ω table value and 3× at 10 Ω gives an $E_{on}$ multiplier of $1 + 2 \cdot (2.7 - 1)/9 \approx 1.38$ at 2.7 Ω. $E_{off}$ and $E_{rr}$ are held at their 1.0 Ω values because no $R_G$-dependent curve for them has been digitized into this model; their $R_G$ dependence is typically much weaker than $E_{on}$'s, but this is unverified here. This is a datasheet-curve interpolation, not a measurement. [ASM] - pin all three energies with a double-pulse test at the populated $R_G = 2.7 \ \Omega$ and +15 V / −9 V gate supplies.

Loss model and assumptions

Assumptions [ASM]

• 3 half-bridge modules, one per phase, symmetrical sharing.
• Modulation index $m = 1.0$, defined as $V_{ph,pk} = m \cdot V_{DC}/2$ (within the linear SVPWM range, which extends to $m = 1.15$ in this convention).
• Sinusoidal phase current $i(\theta) = \hat{I} \cdot \sin \theta$ with $\hat{I} = \sqrt{2} \cdot I_{rms}$.
• Load power factor $\cos \varphi = 0.8$ (traction motor at rated point).
• Junction operating point $T_j = 125 \ ^\circ\text{C}$ (continuous rating is 150 °C; 125 °C leaves margin).
• Switching frequency: per designer intent the PWM is clamped at 6 kHz maximum (v1.2); 2 kHz is retained as a reference point only, 8 kHz is outside the clamped envelope (kept in tables for reference), and 16 kHz is out of scope (will not be used).
• Switching energies include the $R_G = 2.7 \ \Omega$ correction of §2.3: $E_{on}$ multiplied by ≈1.38, $E_{off}$ and $E_{rr}$ unchanged. [ASM]
• Dead time (0.5–4 µs configurable): the extra FWD conduction during dead time adds ≈ $V_{EC} \cdot \langle i \rangle \cdot 2 \cdot t_{dt} \cdot f_{sw} \approx 5$ W per leg (~15 W total) at the 600 A peak (424 A RMS) design point / 2 kHz / 2 µs - under 1 % of total heat, neglected.
• Gate-drive power ($Q_G \cdot \Delta V_{GE} \cdot f_{sw} \approx 0.2$ W per switch, ≈1 W total) is dissipated in the gate resistors/driver, not the module - excluded.
• $E_{on}$ as measured in the datasheet half-bridge circuit already contains the turn-on impact of the opposing diode's reverse recovery; $E_{rr}$ is counted once, in the diode (standard datasheet convention).

Formulas

High-side fundamental duty cycle of one leg (identical for SPWM and SVPWM to first order; third-harmonic injection does not change the fundamental average that sets the IGBT/FWD conduction split):

$$i(\theta) = \hat{I} \cdot \sin \theta \qquad \hat{I} = \sqrt{2} \cdot I_{rms}$$

$$d(\theta) = \frac{1}{2} \cdot \left(1 + m \cdot \sin(\theta - \varphi)\right)$$

Conduction loss per IGBT and per FWD (standard 2-level bridge result, integrating $v(i) \cdot i \cdot d(\theta)$ over the positive current half-wave):

$$P_Q = V_{CE0} \cdot \hat{I} \cdot \left(\frac{1}{2\pi} + \frac{m \cos \varphi}{8}\right) + r_{CE} \cdot \hat{I}^2 \cdot \left(\frac{1}{8} + \frac{m \cos \varphi}{3\pi}\right) \qquad \text{[per IGBT]}$$

$$P_D = V_{EC0} \cdot \hat{I} \cdot \left(\frac{1}{2\pi} - \frac{m \cos \varphi}{8}\right) + r_D \cdot \hat{I}^2 \cdot \left(\frac{1}{8} - \frac{m \cos \varphi}{3\pi}\right) \qquad \text{[per FWD]}$$

Switching loss, averaging the digitized energy curves over the sine half-wave and scaling with bus voltage:

$$P_{sw,Q} = f_{sw} \cdot \frac{V_{DC}}{600 \ \text{V}} \cdot \frac{1}{2\pi} \int_{0}^{\pi} \left[ E_{on}(i(\theta)) + E_{off}(i(\theta)) \right] d\theta \qquad \text{[per IGBT]}$$

$$P_{sw,D} = f_{sw} \cdot \frac{V_{DC}}{600 \ \text{V}} \cdot \frac{1}{2\pi} \int_{0}^{\pi} E_{rr}(i(\theta)) \, d\theta \qquad \text{[per FWD]}$$

Totals for the bridge (6 IGBTs + 6 FWDs) and the heatsink:

$$P_{semi} = 6 \cdot (P_Q + P_D + P_{sw,Q} + P_{sw,D})$$

$$P_{heat} = P_{semi} + P_{cap} \qquad P_{cap} = 40 \ \text{W}$$

$$P_{out} = 3 \cdot V_{ph,rms} \cdot I_{rms} \cdot \cos \varphi = \frac{3 \cdot m \cdot V_{DC} \cdot I_{rms} \cdot \cos \varphi}{2\sqrt{2}}$$

$$\eta = \frac{P_{out}}{P_{out} + P_{heat}}$$

Per-module dissipation (for the thermal chain):

$$P_{mod} = \frac{P_{semi}}{3}$$

Heat vs phase current

Total heat rejected to the heatsink (IGBT + FWD conduction and switching, plus 40 W capacitor heat), $m = 1.0$, $\cos \varphi = 0.8$, $R_G = 2.7 \ \Omega$ ($E_{on} \times 1.38$). Currents are RMS phase current; the design point is 424 A RMS = 600 A peak (bold row). The 600 A RMS row corresponds to 848 A peak, outside the rated envelope, and is retained only as the sweep bound.

Conduction dominates at 2 kHz (switching is only ≈7 % of semiconductor loss at 140 V / 600 A RMS - the 848 A pk envelope-sweep bound row in the table above, not a rating - because the energies scale with $V_{DC}/600 \ \text{V}$). At 320 V / 6 kHz switching is ≈37 % of the 3.2 kW semiconductor loss at the 424 A RMS design point, and at 8 kHz ≈44 % of 3.6 kW. The 40 W capacitor heat is unchanged from v1.0; its derivation and the bank ripple-rating check are in OV-C2-DD-DCLINK-RIPPLE (40 W corresponds to ~240 A RMS operation; the bank loss at 424 A RMS is ~110 - 125 W with the [ASM] ESR ratio there - see that document's comparison section).

Loss breakdown at two reference currents (140 V, 2 kHz, $R_G = 2.7 \ \Omega$):

(The plotted curves are from the v1.0 model at $R_G = 1.0 \ \Omega$; regenerating them against the v1.1 numbers is an open item. The table above is authoritative.)

Inverter efficiency vs phase current

$$\eta = \frac{P_{out}}{P_{out} + P_{heat}} \quad \text{at } m = 1.0, \ \cos \varphi = 0.8, \ 2 \ \text{kHz}, \ R_G = 2.7 \ \Omega$$

including the 40 W capacitor heat.

$$P_{out} = \frac{3 \cdot m \cdot V_{DC} \cdot I_{rms} \cdot \cos \varphi}{2\sqrt{2}}$$

i.e., each bus voltage runs at its rated fundamental output voltage ($P_{out}$ at the 424 A RMS / 600 A peak design point: 37 kW @102 V, 50 kW @140 V, 72 kW @200 V, 115 kW @320 V; table currents are RMS).

At the 140 V nominal bus the efficiency peaks at ≈96.4 % around 150–200 A and falls to 95.3 % at 600 A, because conduction loss grows faster than output power (the $r \cdot I^2$ term). Higher bus voltages are more efficient at the same current because conduction loss is unchanged while output power scales with $V_{DC}$.

(Plotted curves are v1.0 / $R_G = 1.0 \ \Omega$; see the note in §4. Efficiency at 6–8 kHz is lower than tabulated here, by roughly 0.5–1 percentage point at 320 V / 600 A.)

Heatsink sizing

Thermal chain

Steady-state 1-D chain from junction to ambient for the hottest IGBT of a module:

$$T_s = T_{amb} + P_{heat} \cdot R_{th(s-a)}$$

$$T_C = T_s + P_{mod} \cdot R_{th(c-s)}$$

$$T_{j,Q} = T_C + (P_Q + P_{sw,Q}) \cdot R_{th(j-c)Q}$$

$$T_{j,D} = T_C + (P_D + P_{sw,D}) \cdot R_{th(j-c)D}$$

• $R_{th(c-s)} = 13.3$ K/kW typ per module (thermal grease) [DS p.3]
• $R_{th(j-c)Q} = 24$ K/kW max, $R_{th(j-c)D} = 42$ K/kW max [DS p.3]
• Design limits: module baseplate $T_C \le 85 \ ^\circ\text{C}$ at $T_{amb} = 40 \ ^\circ\text{C}$; junction target $T_j \le 125 \ ^\circ\text{C}$ with margin (continuous rating 150 °C [DS]). The 85 °C baseplate limit is also consistent with the firmware NTC monitor (100 °C hard cap on the module-sited NTC). Note the DC-link spreader plate no longer has margin to this limit at the design point: it reaches the FSR-08 derate/SSO band at full load - see §6.3.

Required heatsink thermal resistance

Worst case is 320 V bus (highest switching loss); 140 V nominal shown for reference. All points at $R_G = 2.7 \ \Omega$. 16 kHz is out of scope per designer intent and is no longer evaluated; 8 kHz is shown for reference only (outside the 6 kHz clamped envelope). The 424 A RMS rows are steady-state evaluations at the 600 A peak current; the 330 A RMS row is the continuous rating point (§6.4).

DC-link plate temperature and the capacitor environment (FSR-08 integration)

Framing (v1.3, per designer): the spreader-plate temperature is not itself a design constraint - the plate matters only as the thermal environment of the DC-link capacitors. The governed quantity is the can temperature (105 °C category rating; FSR-08 capacitor channel: derate at 90 °C, SSO at 105 °C), which equals the plate environment plus the can's internal $I^2 \cdot ESR$ hot-spot rise, minus the convection/radiation credit that the conduction-only plate model ignores. The plate numbers below are therefore informational upper bounds on the capacitor environment, not pass/fail criteria.

The DC-link spreader plate sits on the same heatsink and rises up to +35.0 K over the local heatsink surface under its 40 W reference load (thermal paste path, rev-B 6.35 mm plate with the corrected 63 mm rods, OV-C2-DD-DCLINK-THERMAL v1.3; conservative upper bound, convection/radiation neglected; the rev-A 3.18 mm plate with 55 mm rods gave +40.1 K). Taking the maximum $T_s$ for each operating point above (heatsink sized exactly to the 85 °C baseplate limit) and adding the 35.0 K standoff rise:

Against a fixed heatsink the numbers are lower: with the 0.006 K/W margin-target heatsink from the Guidance section, 424 A RMS / 320 V gives $T_s \approx 55 / 59$ °C at 2 / 6 kHz, i.e. plate ≈ 90 / 94 °C; at the 330 A RMS continuous point $T_s \approx 55$ °C, plate ≈ 90 °C (6 kHz). The apparent cooling at higher loss in the table is the sizing-method artifact discussed in v1.1/v1.2: more loss demands a stronger heatsink for the same 85 °C baseplate limit. [ASM] - the plate numbers inherit the ±20 % spreading uncertainty of the DC-link model and its missing convection/radiation credit, and the plate-to-can thermal coupling is unmodeled.

Open hardware fact (v1.3): where the DC-link capacitor NTC is actually mounted - on the spreader plate vs on/near a can - determines what the FSR-08 90/105 °C thresholds measure. If the NTC reads the plate, the thresholds effectively proxy can temperature, and two things follow: (a) on this conservative plate model with the rev-B 6.35 mm plate and the corrected 63 mm rods the 90 °C derate onset sits at ≈330 A RMS continuous (320 V / 6 kHz, 0.006 K/W heatsink) - essentially coincident with the 330 A RMS ripple-based continuous rating, so if the NTC reads the plate, the effective continuous limit remains NTC-placement-dependent at the margin (with the rev-A 3.18 mm plate the onset was ≈220 A RMS and clearly decided the limit); (b) the thresholds can be revisited once can-vs-plate correlation is measured on the dyno (thermal test plan T-05/T-06). Confirm the NTC location from the DC-link board design and record it here and in OV-C2-DD-DCLINK-THERMAL.

Heat-load caveat (v1.3): the +35.0 K reference rise is at the 40 W plate load, corresponding to ≈242 A RMS phase current. The bank loss scales with current squared (74 W at 330 A RMS, 122 W at 424 A RMS, per OV-C2-DD-DCLINK-RIPPLE); if 100 % of it conducted into the plate the bounds would be ≈120 / ≈160 °C at the continuous/peak points - physically excluded by can self-convection and field experience. The conducted fraction is the open measurement (T-05); see OV-C2-DD-DCLINK-THERMAL §"Effect of capacitor heat load".

What governs the rating: the capacitor constraints that actually bind are (a) per-can ripple current vs the frequency-corrected datasheet rating (sets the 330 A RMS continuous rating, §6.4) and (b) can hot-spot temperature vs 105 °C (bounded at the 60 s peak by the minutes-class can time constant). The semiconductor chain has margin throughout ($T_{j,Q} \le 96$ °C vs the 125 °C target at every table point). The plate/plate-model temperature is retained as the conservative bound on the capacitor environment and as the correlation target for the dyno NTC calibration - not as a rating constraint.

Continuous and peak current rating (v1.3)

Ratings are stated in peak phase current per the IEC 61800-2 style overload convention: a continuous rating plus a time-limited peak, where peak = 600 A for 60 s (424 A RMS). Throughout this document the analysis currents are RMS, with the peak equivalent noted ($\hat{I} = \sqrt{2}\,I_{rms}$). The designer's reservation about peak differing from continuous is addressed by making the peak verifiable: it carries an explicit time limit and a windowed RMS duty requirement (below), so it is a testable envelope, not a marketing number.

Continuous rating: 465 A (330 A RMS) at 6 kHz PWM, 40 °C ambient, with the 0.006 K/W margin-target heatsink. The constraints at 6 kHz:

The rating is set by the capacitor ripple: the electrolytic bank binds at 330 A RMS; the plate and the semiconductors do not. At 330 A RMS / 320 V / 6 kHz the model gives $P_{heat} = 2471$ W, $T_s \approx 55$ °C, plate upper bound ≈ 90 °C (rev-B 6.35 mm plate, 63 mm rods, +35.0 K reference rise - at the derate onset on this conservative bound), $T_{j,Q} \approx 93$ °C (far inside the 125 °C target). The rating is stated at the worst-case bus (320 V).

This is a conservative analytical bound, not a measured rating. The conservatisms, itemized:

1. The plate model routes 100 % of capacitor heat through the standoff path and credits no convection/radiation; the real rise is below +35.0 K (OV-C2-DD-DCLINK-THERMAL, OV-C2-DD-DCLINK-RIPPLE §"Interpretation").
2. The ripple/ESR model uses an assumed ESR ratio (0.15 × tan δ ceiling) with no published UCS impedance curve; ±50 % would not be surprising (OV-C2-DD-DCLINK-RIPPLE [ASM]).
3. The ripple current formula is a stiff-source upper bound; a real battery/dyno source absorbs part of the ripple.
4. Worst-case continuous duty at $m = 1.0$, $\cos \varphi = 0.8$, 40 °C ambient; no credit for part-load, cooler ambients, or cans running below their 105 °C category temperature (the ripple check is performed at the 105 °C rating; Nichicon publishes no temperature coefficient for UCS, so no credit is taken for cooler cans).
5. Field experience at 100 - 200 A phase current shows the cans running cool, which is consistent with the model at those currents and suggests the bound has real margin at rated current too.

Measured data supersedes this bound when available; the two pinning measurements are listed in OV-C2-DD-DCLINK-RIPPLE §"Continuous and peak rating" (can-branch ripple measurement and can/plate NTC correlation at load).

Peak rating: 600 A (424 A RMS) for 60 s at ≤ 6 kHz, validated by thermal time constants:

• Junction (fast, seconds class): the IGBT junction reaches essentially its steady-state rise well within 60 s; $T_{j,Q} = 95$ °C and $T_{j,D} = 89$ °C at 424 A RMS / 320 V / 6 kHz vs the 125 °C design target. Not binding.
• Heatsink and plate (slow, minutes class [EST]): on the 0.006 K/W heatsink the steady-state plate bound is ≈ 90 °C at the continuous point and ≈ 94 °C at the peak point (rev-B plate, 63 mm rods) - a delta of only ~4 - 5 K, of which a 60 s excursion captures 10 - 33 % (3 - 10 min plate+heatsink time constant [EST]): end-of-peak plate ≈ 90 - 91 °C, around the 90 °C derate onset on this conservative bound.
• Capacitor cans (slow, minutes class [EST]): at 424 A RMS the per-can ripple is 3.61 A RMS, 1.28x the 6 kHz rating (≈1.6x rated $I^2 \cdot ESR$ loss). This exceeds the continuous ripple rating but is time-limited: the winding hot-spot responds with a minutes-class time constant, so a 60 s peak captures only a fraction of the incremental rise from the continuous point; the per-event hot-spot excursion is single-digit K class [EST]. The accumulated lifetime cost is bounded by the duty requirement below. Pin with the can NTC during dyno (thermal test plan T-05/T-06).
• Duty requirement (makes the peak verifiable): RMS phase current over any rolling 10-minute window shall not exceed the 330 A RMS continuous rating. Worked example: after a full 60 s / 424 A RMS peak, the following 9 minutes must stay at ≲ 318 A RMS; shorter or lower peaks relax this proportionally. Firmware shall enforce the windowed RMS limit. With the rev-B plate the end-of-peak plate bound (≈90 - 91 °C) sits at the FSR-08 90 °C derate onset, so the derate response may graze onset on a compliant peak if the NTC reads the plate; the firmware shall tolerate this bounded excursion rather than SSO. If the NTC is can-mounted, the thresholds apply to the can estimate per §6.3.

Why peak ≠ continuous, honestly: continuous 600 A (424 A RMS) operation exceeds the electrolytic ripple rating (1.28x at 424 A RMS), and fixing that costs hardware this chassis does not have (≈77 cans to hold the 6 kHz rating at 424 A RMS, or higher-ripple cans / a film bank - see OV-C2-DD-DCLINK-RIPPLE). The 60 s peak covers real traction duty (acceleration, gradeability, obstacle starts) where high current is inherently transient, while the continuous rating keeps the capacitors inside their datasheet endurance. If a future revision needs higher continuous current, the levers are in OV-C2-DD-DCLINK-RIPPLE (bank changes) plus the measurement campaign that may raise the analytical bound without any hardware change.

Guidance

• Peak 600 A pk (424 A RMS) / 320 V (60 s): $R_{th(s-a)} \le 0.0095$ K/W (9.5 mK/W) at the 6 kHz clamp for the whole three-module heatsink assembly, 40 °C ambient (8.0 mK/W at the out-of-envelope 8 kHz point; 14.1 mK/W at the 2 kHz reference). With ≥25 % engineering margin (grease ageing, digitization/typ-value uncertainty, module-to-module variation, fouling), the design target is ≈ 0.007 K/W or better; the margin-target value used for the rating analysis in §6.4 is 0.006 K/W, i.e. ≈37 % margin against the 6 kHz peak requirement. All of these are outside natural-convection territory (a very large natural-convection sink is ≈0.1–0.5 K/W); 6 kHz at high current requires a liquid cold plate.
• Continuous 330 A RMS (465 A pk) / 320 V / 6 kHz (rated point): $R_{th(s-a)} \le 0.0139$ K/W for the baseplate constraint; with the 0.006 K/W margin-target heatsink $T_s \approx 55$ °C and the DC-link plate upper bound is ≈ 90 °C, at the 90 °C FSR-08 derate onset on this conservative bound (rev-B plate, 63 mm rods) - see §6.3/§6.4.
• The junction rise is small at the design point ($T_{j,Q} \approx 95 \ ^\circ\text{C}$ at $T_C = 85 \ ^\circ\text{C}$, ≈30 °C margin to the 125 °C target) because $R_{th(j-c)}$ is only 24 K/kW; the baseplate ≤ 85 °C constraint, not the junction, sizes the heatsink. Per-switch dissipation of ≈400 W at 424 A RMS / 320 V / 2 kHz (≈530 W at 6 kHz) is also well inside the module's 6250 W total dissipation rating (datasheet p.2).
• The capacitor bank, not the semiconductors, sets the real full-load limit - the continuous rating is ripple-set (§6.4), and the plate model is the conservative bound on the capacitor environment (§6.3). Any heatsink decision shall be checked against the plate/can temperature, not only the baseplate limit.
• Mounting: thermal grease per datasheet note 6 ($\lambda = 3.0$ W/(m·K), 50 µm), M6 mounting torque 3.5–4.5 N·m (datasheet p.3), baseplate flatness ≤ 200 µm on the centerlines. Verify the three modules are placed so each sees comparable sink temperature.

Sensitivity and notes

• 6 kHz clamp: switching loss scales linearly with $f_{sw}$. At the 600 A RMS (848 A pk, envelope-sweep bound) / 320 V point, total heat rises from 3.8 kW (2 kHz) to 5.0 kW (6 kHz) and 5.5 kW (8 kHz), and the heatsink requirement tightens from 7.3 to 4.7 / 3.7 mK/W (values unchanged; §6.2 sweep-table row). Per designer decision (v1.2) the PWM is clamped at 6 kHz; 8 kHz is dropped (it also sits next to the ~7.8 kHz electrolytic-branch series resonance, OV-C2-DD-DCLINK-RIPPLE) and 16 kHz is out of scope. 6 kHz at high current means liquid cooling.
• Lower power factor: total heat is nearly unchanged (the IGBT $V_0$ term falls while the FWD share rises; at $\cos \varphi = 0.5$, 600 A / 140 V / 2 kHz, $P_{heat} \approx 3.46$ kW vs 3.49 kW at $\cos \varphi = 0.8$), but output power falls proportionally with $\cos \varphi$, so efficiency drops (≈92.8 % at $\cos \varphi = 0.5$, 600 A / 140 V) and heat per kW delivered rises. Regenerative braking ($\cos \varphi < 0$) shifts loss toward the FWDs - $R_{th(j-c)D} = 42$ K/kW keeps the diode junction ≈5 °C cooler than the IGBT at rated point, so this is not binding.
• Typical vs maximum device values: conduction uses typical chip $V_{CE(sat)}/V_{EC}$; the max terminal values are ≈10–15 % higher, and $R_{th(c-s)}$ is a typical (not max) value. The ≥25 % heatsink margin policy covers this.
• 600 A RMS operation: at 600 A RMS the sine peak is 848 A, above the module's 600 A DC rating (at $T_C = 144 \ ^\circ\text{C}$) but within the 1200 A repetitive pulse rating. Per §6.4 (v1.3) the adopted rating is 465 A (330 A RMS) continuous / 600 A (424 A RMS) peak for 60 s: the continuous rating is set by the capacitor ripple (the electrolytic bank binds at 330 A RMS; the plate and the semiconductors do not), and the rated peak operating point is 424 A RMS (600 A pk) for 60 s - the 424 A RMS rows in the tables. The 600 A RMS rows are the 848 A pk envelope-sweep bound, outside the rated envelope, and are retained only as the sweep bound, not as an operating point. Full-load dyno/thermal validation of both ratings is still pending - treat the 600 A RMS rows as the sweep sizing bound, not a validated rating.
• Gate resistance: all switching energies now include the populated $R_G = 2.7 \ \Omega$ correction ($E_{on} \times 1.38$, linear interpolation of the datasheet p.7 $E$ vs $R_G$ curve between 1 Ω and the ≈3× point at 10 Ω; $E_{off}$/$E_{rr}$ unscaled). This is a datasheet-curve interpolation, not a measurement, and the $E_{off}$/$E_{rr}$ $R_G$-dependence is unmodeled [ASM]. Pin $E_{on}$, $E_{off}$, and $E_{rr}$ with a double-pulse test at $R_G = 2.7 \ \Omega$, +15 V / −9 V, representative bus voltage and current; re-run this analysis with the measured energies.
• Low-current extrapolation: below ≈100 A the $E_{rr}/E_{off}$ curve extrapolation carries the constant offsets ($E_{off} \approx 8.7$ mJ, $E_{rr} \approx 12$ mJ); the resulting low-current, high-frequency numbers (e.g., 50 A / 8 kHz) are the least accurate in this document, ±15 %.
• Not modeled: stray-inductance overshoot losses, module NTC self-heating, busbar/terminal ohmic heating into the heatsink (small vs 3.5 kW), and heatsink thermal spreading between modules (left to the heatsink detailed design). Ambient 40 °C is assumed at the heatsink inlet; inside a sealed chassis, derate accordingly.
• Firmware tie-in: the real-time loss estimator uses the same model structure ($V_{ce0}/R_{ce}$ conduction + $E_{on}/E_{off}$ curves + $R_{th}$ chain); the parameters in §2.3 are the recommended calibration set for it.

Revision History

This is a design estimate for heatsink sizing, to be validated by test on the assembled inverter.